The present invention relates to a method for making a heterojunction bipolar transistor by stacking epitaxial semiconductor layers, and more particularly such a method comprising steps consisting of epitaxially growing from a support at least one collecting layer (for an E-up configuration) and one emitting layer (for a C-up configuration) respectively, at least one base layer, and at least one emitting layer and one collecting layer respectively.
A heterojunction bipolar transistor is made up of a stack of three semiconductor regions: emitter, base and collector, wherein the emitter has a forbidden energy gap wider than that of the base. Its lateral extension (in each of the planes of the preceding regions) is made up of two zones: one, called intrinsic or active, is defined by the surface of the emitter-base junction; the other, called extrinsic or parasitic, is located in the periphery of the former, between it and the electrical contacts (base and collector) of the transistor. The speed of the HBT is optimised by jointly reducing, on the one hand, the transit time of the carriers between the emitter and the collector and, on the other hand, the parasitic effects (serial resistors and capacitors) associated with the extrinsic zone. Transit time can be reduced through various approaches, widely described in existing literature: ballistic injection in the base (abrupt heterojunction type I), thin base, doping and/or concentration gradient in the base (quasi-electric field), thin collector, ballistic injection in the collector (type-II abrupt heterojunction), Schottky collector, etc. The reduction of parasitic effects is, in general terms, obtained by reducing the width of the peripheral zone and by using suitable materials (i.e. low resistivity for access resistors, low electric permittivity for the capacitors). The present invention makes it possible to reduce the base-collector capacity by means of the reduction of transit time described above.
The invention effectively makes it possible to produce HBTs, in particular with a GaAsSb base layer, having both a thin and limited base and a deeply underetching base-collector junction. These two points, until now incompatible in the same transistor, allow for a considerable improvement of its dynamic performance. The first point mainly affects the conditions of electronic transport (band discontinuity at the emitter-base interface, effective mass of the carriers, resistivity of the base, resistivity of the base contact, etc.) while the second point enables a drastic reduction of the base-collector parasitic capacity (i.e. associated with the extrinsic part of the base-collector junction), the parasitic capacity limiting the operating frequency of the HBT.
GaAsSb HBTs are known from the document “Ultra-high performance staggered lineup (“Type-II”) InP/GaAsSb/InP npn Double Heterojunction Bipolar Transistor” C. R. Bolog nesi, M. W. Dvorak, N. Matine, O. J. Pitts and S. P. Watkins, Jpn. J. Appl. Phys. Vol. 41 Part 1(2B) 1131 (2002). These transistors have shown remarkable results (fT=fmax=300 GHz) and clear progress compared with the state of the art at the time, obtained with InP/InGaAs structures. The same authors have shown that the antimony composition used in the base layer was considerably lower than the concentration ensuring lattice match with InP ([Sb]=0.5). The technology used has limited the underetching of the collecting layer to 750 nm under the base contact, while the latter overhangs the emitter finger by 1.5 μm. A comparison between the experimental results and those resulting from the simulation shows clearly superior performance (i.e. >500 GHz) for a unit report of the emitter-base and base-collector junction areas. Finally, the contribution of the GaAsSb to the speed of the transistor is clearly established.
The document “InP/InGaAs SHBTs with 75 nm collector and fT>500 GHz” W. Hafez, Jie-Wei Lai and M. Feng, Electron. Lett. 39(20) (2003) also describes an InP/InGaAs stack allowing frequencies in excess of 500 GHz to be obtained. These results have shown the importance of reducing both the electron transit time by reducing the thickness of the various semiconductor layers (in particular the collecting layer) and the lateral dimensions of the component. A GaAsSb HBT typically has the structure shown in table 1 below.
Throughout the production of the transistor, the InP layer of the collector is laterally etched to a considerable depth in order to reduce the base-collector capacity. This etching is only possible by chemical means, as no dry etching is sufficiently anisotropic for this purpose. The very high selectivity of InP chemical etching is used compared with arsenides (in this case GaAsSb and InGaAs) in, for example, a solution of H3PO4:HCl.
As the base is very thin (typically between 20 and 50 nm), it is not rigid enough to support itself over a sufficient length (typically 1.5 to 2 μm). The known manufacturing process therefore contemplates preserving the emitting layer E with the same dimensions as the base B during the underetching of the InP layer located in the collector C (FIG. 1a). At this stage in the progress of the method, the structure as known until now is seriously flawed if the GaAsSb base has an antimony content of less than 50%. Indeed, as the emitter (InP or InGaAlAs) must necessarily be epitaxially grown at the lattice match with InP, there is a considerable gap in the lattice parameter (lack of lattice match) between the two layers constituting the base overhang (E and B FIG. 1a) overhanging the InP underetching. Under the action of this constraint, the overhang deforms (FIG. 1b) and can create a short-circuit between the base and the collector and, in any case, make it difficult to introduce resin between the base layer and the collector contact layer CC.
For these reasons, the skilled person in the art generally limits himself only to etching stacks made with materials that have lattice match between them, which is to say, stacks that do not have any constraints. This is the disadvantage that the present invention aims to solve by introducing a new layer of InGaAlAs quaternary in the collector. The symmetry (even approximate) of the stack of layers in the base overhang balances the constraints and considerably reduces deformations. In addition, it is known to modify the composition of the semiconductor to make the base layer, so as to considerably modify the electronic transport properties in the active zone of the transistor.
The invention guarantees compatibility between the performance of a deep underetching and the existence of a constraint in the base layer. The invention also aims to make it possible to use, in a HBT, a base made up of a semiconductor alloy in which the molecular arrangement (depending on the composition of the alloy) does not correspond to the lattice match required by the emitting or collecting layer. For example, the invention supports the use of a base made from GaAsSb alloy, with an antimony ratio higher or lower than 50%.
American patent application US-2004/0227155 A1 is known in the prior art, which suggests introducing an In Ga As Sb underlayer between the base layer and the collecting layer so as to improve the properties of the HBT. The HBT thus made does not have any constraints relating to a lack of lattice match, even before introducing the underlayer. Also known is patent application US-2004/0214401 A1, which describes a method for passivating a HBT by epitaxy of a semiconductor on its entire surface. Finally, U.S. Pat. No. 6,165,859 is known, which describes the production of low-resistivity contacts using Pd/Pt/Au.
The invention relates above all to a method for making a heterojunction bipolar transistor by stacking epitaxially grown semiconductor layers, comprising steps consisting of epitaxially growing from a support at least one collecting layer and one emitting layer respectively, at least one base layer, and at least one emitting layer and one collecting layer respectively, said layers having compositions producing a lattice match fault causing deformations. According to the invention, the step consisting of epitaxially growing said collecting layer and emitting layer respectively comprises sub-steps consisting of epitaxially growing, in contact with said base layer, at least one underlayer for balancing the constraints and reducing the deformations and, in particular, an underlayer with substantially the same composition as said emitting layer and collecting layer respectively and at least one second underlayer on the side opposite said base layer in relation to said first underlayer.
In a specific embodiment of the invention, for making a transistor in which said emitting layer and said collecting layer respectively comprise two underlayers including a first underlayer in contact with the base layer and a second underlayer on the side opposite said base layer in relation to said first underlayer, said first underlayer of the collector and the emitter respectively has substantially the same composition as the first underlayer of the emitter and the collector respectively. The invention also relates to a heterojunction bipolar transistor comprising a support and, epitaxially grown from this support, at least:
one collecting layer and one emitting layer respectively;
at least one base layer; and
one emitting layer and one collecting layer respectively; said layers having compositions producing a lattice match fault causing deformations.
According to the invention, said collecting layer and emitting layer respectively comprise:
at least one first underlayer in contact with said base layer, for balancing the constraints caused by said emitting layer and collecting layer respectively in particular an underlayer with substantially the same composition as said emitting layer and collecting layer respectively; and
at least one second underlayer on the side opposite said base layer in relation to said first underlayer.
In a specific embodiment, said second underlayer is underetched to a minimum lateral extension comprised between that of the base and that of the emitter-base and collector-base junction respectively. Optimally, this lateral extension will be of the order of that of the emitter-base and collector-base junction respectively. In practice, however, it will be slightly larger, but naturally smaller than that of the base.
Also in a specific embodiment, said emitting layer and collecting layer respectively comprise:
at least one first underlayer in contact with said base layer, substantially of said composition; and
at least one second underlayer on the side opposite said base layer in relation to said first underlayer.
In a specific embodiment, said second underlayer is underetched to a lateral extension of the order of that of the emitter-base and collector-base junction respectively.
Said emitting layer and collecting layer respectively can, in particular, comprise:
at least one first underlayer in contact with said base layer, substantially of said composition; and
at least one second underlayer on the side opposite said base layer in relation to said first underlayer.
The invention also relates to a method for making a transistor such as previously described, said method comprising the steps consisting of:
epitaxially growing said layers and underlayers;
etching the layers above said emitting layer and collecting layer respectively;
said method also comprising the steps consisting of:
underetching said second underlayer and of the collector and emitter respectively;
filling the space left by said underetching between said first underlayer of the collector and emitter respectively and the layer located under the second underlayer with an insulating material; and
etching said emitting layer and collecting layer respectively.
In one specific embodiment, to make a transistor comprising a contact layer of the emitter and collector respectively and a metal contact, this method comprises the step consisting of encapsulating said contact of the emitter and the collector respectively and the metal contact in a material to protect it against etching. To make a transistor in which said emitting layer and collecting layer respectively comprise two underlayers in which a first underlayer is in contact with the base layer and a second underlayer is on the side opposite said base layer in relation to said first underlayer, the step consisting of etching the layers above said emitting and collecting layer respectively is followed by a step consisting of etching the second underlayer of the emitter and collector respectively. In a specific embodiment, the encapsulation step includes encapsulating the non-etched part of the second underlayer of the emitter and collector respectively, placed between the first underlayer of the emitter and collector respectively and the contact layer of the emitter and collector respectively. The invention also relates to a transistor such as described above, wherein:
said base layer is made from GaAsSb;
said first underlayers are made from InGaAlAs; and
said second underlayers are made from InP.
Finally, the invention relates to a use of underlayers for balancing constraints generated by epitaxially grown layers which are stacked on top of one another, the stacking having lattice match faults between the epitaxially grown layers due to their composition and, in particular, due to the composition of the base layer.